HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 80
HFIXF1110CC.B2 Q E000
Manufacturer Part Number
HFIXF1110CC.B2 Q E000
Description
Manufacturer
Intel
Datasheet
1.HFIXF1110CC.B2_Q_E000.pdf
(183 pages)
Specifications of HFIXF1110CC.B2 Q E000
Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant
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Intel
07-Oct-2005
80
®
Figure 16. Data Validity Timing
Figure 17. Start and Stop Definition Timing
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
5.4.4.4.1
A High-to-Low transition of I
precede any other command (see
5.4.4.4.2
A Low-to-High transition of the I
sequence, the stop command places the E
Figure
5.4.4.4.3
All addresses and data words are serially transmitted to and from the optical module in 8-bit words.
The optical module E
happens during the ninth clock cycle (see
I
2
C_DATA
I
2
I
C_CLK
2
17).
C_DATA
I
2
C_CLK
Intel
Start Condition
Stop Condition
Acknowledge
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
2
PROM sends a zero to acknowledge that it has received each word, which
Order Number: 250210, Revision: 009
START
2
C_DATA, with I
Figure
2
DATA STABLE
C_DATA with I
17).
2
Figure
PROM in the optical in a standby power mode (see
2
C_CLK High, is a start condition that must
CHANGE
18).
DATA
2
C_CLK High is a stop condition. After a Read
DATA STABLE
STOP
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