HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 175

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

8.5.8
Datasheet
Table 104. SPI4-2 TX Synchronization ($ 0x703)
Table 105. SerDes Tx Driver Power Level Ports 0-6 ($ 0x784)
SerDes Register Overview
Table 105
Block at base location 0x780 which contain the control and status for the ten SerDes interfaces on
the IXF1110.
Register Description: SPI4-2 synchronization DIP-4 counters.
Register Description: Allows selection of various programmable drive strengths on each of
the SerDes ports.
NOTE: Refer to
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. When Periodic Training is enabled, the actual count of DIP4 errors required to lose synchronization is 1
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
31:16
31:28
27:25
24:21
20:16
15:12
15:8
11:8
Bit
7:0
less than the programmed value in this register. Therefore, this value should always be programmed to be
1 more than the desired value and should never be programmed to either 0 or 1.
Bit
7:4
3:0
power levels.
DIP4_Errors
DIP4_UnLock
DIP4_Lock
Intel
Reserved
DRVPWR6[3:0] Encoded input that sets Power Level for Port 6
DRVPWR5[3:0] Encoded input that sets Power Level for Port 5
DRVPWR4[3:0] Encoded input that sets Power Level for Port 4
DRVPWR3[3:0] Encoded input that sets Power Level for Port 3
DRVPWR2[3:0] Encoded input that sets Power Level for Port 2
DRVPWR1[3:0] Encoded input that sets Power Level for Port 1
DRVPWR0[3:0] Encoded input that sets Power Level for Port 0
through
®
Name
Table 21, “SerDes Driver TX Power Levels” on page 72
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Name
Table 107 on page 176
2
Order Number: 250210, Revision: 009
Reserved
DIP4_Errors is the total number of DIP4
errors detected since this register was last
read.
DIP-4_Unlock is a SPI4-2 parameter
specifying the number of incorrect DIP4
fields to be detected to declare loss of
synchronization and drive the TSTAT[1:0]
bus with framing.
Number of consecutive correct DIP4 results
to achieve synchronization and end training
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Description
Description
define the contents of the SerDes Register
for valid SerDes
Type
CoR
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
1
1
0X00000000
0x00000420
07-Oct-2005
Default
Default
0x0000
1101
1101
1101
1101
1101
1101
1101
0x04
0x20
0x0
175