HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 167

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Table 96. TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D) (Sheet 2 of 3)
TX FIFO MAC
Transfer
Threshold Port 4
TX FIFO MAC
Transfer
Threshold Port 5
TX FIFO MAC
Transfer
Threshold Port 6
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9):
3. For proper operation of the IXF1110, the MAC transfer threshold must be set to greater than the MaxBurst1
Bits 31:13 - Reserved and R.
Bits 12:0 - Described above.
on the SPI4-2.
Name
2
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Description
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Order Number: 250210, Revision: 009
3
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Address
0x61A
0x618
0x619
Type
R/W
R/W
R/W
1
0x00000100
0x00000100
0x00000100
07-Oct-2005
Default
167