HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 101

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

6.4
6.4.1
6.4.1.1
Datasheet
Note: Users should ensure that flow control is enabled to prevent RX FIFO overflows. If an RX FIFO
Note: In systems where the SYS_RES_L pin is driven from a single board-wide reset signal, the switch
overflow occurs, data is sent out on the SPI4-2 interface regardless of the
Drop Enable ($ 0x59F)”
upstream device that this data is corrupted.
Reset and Initialization
When powering up the IXF1110 MAC, the hardware reset signal (SYS_RES_L) should be held
active Low for a minimum of 100 ns after all of the power rails have fully stabilized to their
nominal values and the input clocks have reached their nominal frequency (TDCLK = 400 MHz,
CLK125 = 125 MHz, and CLK50 = 50 MHz).
or network processor only comes out of reset at the same time as the IXF1110 MAC, or possibly
later. This means the TDCLK may not be applied to theIXF1110 MAC when the SYS_RES_L pin
is released. However, the system designer must ensure that the switch or network processor does
not output TDCLK until it is stable and has reached its nominal operating frequency. Failure to
apply a stable TDCLK to the IXF1110 MAC can result in the IXF1110 MAC training on a non-
stable clock thus causing DIP4 errors and data corruption. This will require a re-training once the
TDCLK is stable.
When the TDCLK is applied after the reset pin is released, a built-in feature in the IXF1110 MAC
reactivates the internal reset once TDCLK is applied. The IXF1110 MAC extends this hardware
reset internally to ensure synchronization of all internal blocks within the system. The internal reset
is extended for a minimum of 4.11 ms after all clocks are stable.
The device is correctly initialized at this point and ready for use. Clocks start to appear at the
relevant device ports and the SPI4-2 interface begins to source a training pattern on the receive side
while waiting for a training pattern on the transmit side. The SPI4-2 interface synchronizes with the
connected switch or network processor per the SPI4-2 Specification.
The CPU accesses can begin to configure the device for any existing user preferences desired.By
default, all ports on the IXF1110 MAC are enabled after power-up. The device is ready for use at
this time if the default settings are to be used. Otherwise, access the required registers via the CPU
interface and configure the control registers to the required settings.
SPI4-2 Initialization
RX SPI4-2
After reset or Power-up the RX SPI4-2 interface will start to source training patterns on the data
bus to the upstream SPI4-2 device. The IXF1110 MAC will continue to send the training patterns
until a valid calendar is sent on RSTAT[1:0] from the upstream device to the IXF1110 MAC. At
this point, synchronization with the upstream device is complete and the IXF1110 MAC will start
to send data once data is available and a credit has been granted from the RSTAT[1:0] bus.
When synchronization is completed, bit 13 of the
completion, bit 13 is “0”, indicating the IXF1110 MAC is sending out training patterns on the RX
SPI4-2 data bus.
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
settings. The data is marked with an EOP abort code to inform the
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
“SPI4-2 RX Calendar ($ 0x702)”
“RX FIFO Errored Frame
is “1”. Before
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