HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 133

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HFIXF1110CC.B2 Q E000

Manufacturer Part Number
HFIXF1110CC.B2 Q E000
Description
Manufacturer
Intel
Datasheet

Specifications of HFIXF1110CC.B2 Q E000

Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant
8.5.1
Datasheet
Table 60. Station Address Low ($ Port_Index + 0x00)
Table 61. Station Address High ($ Port_Index + 0x01)
Table 62. FDFC Type ($ Port_Index + 0x03)
Table 63. FC TX Timer Value ($ Port_Index + 0x07)
MAC Control Registers
Table 60
with each MAC port. The register address is ‘Port_index + 0x**’, where the port index is set at
any value from 0x000 through 0x500. All registers are 32 bits.
31:16
15:0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
31:16
31:16
31:0
15:0
15:0
Bit
Bit
Bit
Bit
through
Intel
Station
Address Low
Reserved
Station
Address High
Reserved
FDFC Type
Reserved
FC TX Timer
Value
®
Name
Name
Name
Name
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Table 76 on page 140
Order Number: 250210, Revision: 009
Reserved
Reserved
Reserved
Source MAC address bits 31-0.
This address is inserted in the source address field
when transmitting Pause frames, and is also used to
compare against unicast Pause frames at the
receiving side.
Source MAC address bits 47-32.
This address is inserted in the source address field
when transmitting Pause frames, and is also used to
compare against unicast Pause frames at the
receiving side.
Contains the value of the type field transmitted in an
internally generated flow control (pause) frame.
Internally generated flow control frames are
generated via the external pause interface or when
the RX FIFO exceeds its high watermark.
The pause length sent to the receiving station in 512
bit times
Intel
provide details on the control and status registers associated
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Description
Description
Description
Description
Type
Type
Type
Type
R/W
R/W
R/W
R/W
R
R
R
1
1
1
1
0x00000000
07-Oct-2005
Default
Default
Default
Default
0x005E
0x0000
0x0000
0x0000
0x8808
0x0000
133

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