MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 12

MT45W8MW16BGX-701 IT

Manufacturer Part Number
MT45W8MW16BGX-701 IT
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT45W8MW16BGX-701 IT

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
Page Mode READ Operation
Figure 7:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
Page Mode READ Operation (ADV# LOW)
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
performed, then adjacent addresses can be read quickly by simply changing the low-
order address. Addresses A[3:0] are used to determine the members of the 16-address
CellularRAM page. Any change in addresses A[4] or higher will initiate a new
time. Figure 7 shows the timing for a page mode access. Page mode takes advantage of
the fact that adjacent addresses can be read in a shorter period of time than random
addresses. WRITE operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held LOW. CE# must
be driven HIGH upon completion of a page mode access. WAIT will be driven while the
device is enabled and its state should be ignored. Page mode is enabled by setting
RCR[7] to HIGH. ADV# must be driven LOW during all page mode read accesses.
Due to refresh considerations, CE# must not be LOW longer than
ADDRESS
LB#/UB#
DATA
WE#
OE#
CE#
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
D1
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D2
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D3
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©2004 Micron Technology, Inc. All rights reserved.
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