MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 31

• Manufacturer Part Number: MT45W8MW16BGX-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Refresh Configuration Register (RCR)
PAR (RCR[2:0]) Default = Full Array Refresh
Figure 24:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
All must be set to “0”
RCR[19]
RCR[7]
0
1
0
0
1
Reserved
Refresh Configuration Register Mapping
A[22:20] A[19:18]
22–20
RCR[18]
Page mode disabled (default)
Page mode enable
0
0
1
Register
Select
19–18
Page Mode Enable/Disable
Select RCR
Select BCR
Select DIDR
All must be set to “0”
Register Select
The RCR defines how the CellularRAM device performs its transparent self refresh.
Altering the refresh parameters can dramatically reduce current consumption during
standby mode. Page mode control is also embedded into the RCR. Figure 24 describes
the control bits used in the RCR. At power-up, the RCR is set to 0010h.
The RCR is accessed with CRE HIGH and A[19:18] = 00b or through the register access
software sequence with DQ = 0000h on the third cycle. (See “Registers” on page 17.)
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start at either the beginning or the end of the address map. (See Table 12
on page 36.)
Reserved
17–8
A[17:8]
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
Page
7
A7
Setting is ignored
(Default 00b)
Reserved
6
A6
5
A5
RCR[4]
DPD
31
0
1
4
A4
Must be set to “0”
Reserved
DPD enable
DPD disable (default)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
A3
Page/Burst CellularRAM 1.5 Memory
Deep Power-Down
RCR[2]
0
0
0
0
1
1
1
1
2
A2
RCR[1]
1
1
1
0
0
0
0
1
PAR
1
A1
RCR[0]
0
1
1
0
0
1
1
0
©2004 Micron Technology, Inc. All rights reserved.
Top 1/8 array
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
A0
0
Refresh Coverage
Address Bus