MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 8

• Manufacturer Part Number: MT45W8MW16BGX-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 2:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
Asynchronous Mode
BCR[15] = 1
Burst Mode
BCR[15] = 0
Read
Write
Standby
No operation
Configuration register
write
Configuration register
read
DPD
Async read
Async write
Standby
No operation
Initial burst read
Initial burst write
Burst continue
Burst suspend
Configuration register
write
Configuration register
read
DPD
Bus Operations
Notes:
power-down
power-down
1. CLK must be LOW during async read and async write modes; and to achieve standby power
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
6. V
7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the
Standby
Standby
Power
Power
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Deep
Deep
Idle
Idle
during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend.
select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are
affected.
isolated from any external influence.
rent.
maintained until CE# transitions from HIGH to LOW.
equivalent of a single-word burst (as indicated by WAIT).
IN
= V
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
CC
Q or 0V; all device balls must be static (unswitched) in order to achieve standby cur-
CLK
CLK
X
L
L
L
L
L
L
L
L
L
L
L
L
1
1
ADV#
ADV#
X
X
X
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
CE#
CE#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
8
OE#
OE#
H
X
X
X
H
X
X
X
X
X
X
H
H
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
WE#
WE#
H
X
X
H
X
H
X
X
H
X
X
H
X
L
L
L
L
L
CRE
CRE
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
LB#/
LB#/
UB# WAIT
UB# WAIT
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
High-Z
High-Z
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
©2004 Micron Technology, Inc. All rights reserved.
2
2
DQ[15:0]
DQ[15:0]
Data-in or
Data-out
Data-out
Data-out
reg. out
reg. out
Data-in
Config.
Data-in
Config.
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
X
X
X
3
3
Notes
Notes
5, 6
4, 6
5, 6
4, 6
4, 8
4, 8
4, 8
4, 8
8, 9
8, 9
4
4
7
4
4
7