MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 28

• Manufacturer Part Number: MT45W8MW16BGX-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 21:
Latency Counter (BCR[13:11]) Default = Three Clock Latency
Initial Access Latency (BCR[14]) Default = Variable
Table 5:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
DQ[15:0]
BCR[13:11] Latency Configuration Code
Others
WAIT
WAIT
010
011
100
CLK
2 (3 clocks)
3 (4 clocks)—default
4 (5 clocks)
Reserved
Variable Latency Configuration Codes
WAIT Configuration During Burst Operation
Notes:
Notes:
1. Non-default BCR setting: WAIT active LOW.
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. For allowable latency
codes, see Table 5, Figure 22 on page 29, Table 6 on page 29, and Figure 23 on page 30.
Variable initial access latency outputs data after the number of clocks set by the latency
counter. However, WAIT must be monitored to detect delays caused by collisions with
refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for
worst-case refresh collisions. The latency counter must be configured to match the
initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed
initial latency. The burst begins after the number of clock cycles configured by the
latency counter. (See Table 6 and Figure 23.)
1. Latency is the number of clock cycles from the initiation of a burst operation until data
appears. Data is transferred on the next clock cycle.
D0
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
D1
Normal
—
2
3
4
Latency
D2
Collision
Refresh
28
1
—
4
6
8
End of row
D3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
104 (9.62ns) 104 (9.62ns) 80 (12.5ns)
66 (15.0ns)
133 (7.5ns)
-7013
—
Max Input CLK Frequency (MHz)
66 (15ns)
Don’t Care
-701
—
—
©2004 Micron Technology, Inc. All rights reserved.
BCR[8] = 0
Data valid in current cycle.
BCR[8] = 1
Data valid in next cycle.
52 (19.2ns)
-708
—
—
40 (25ns)
66 (15ns)
-856
—
—