MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 7

• Manufacturer Part Number: MT45W8MW16BGX-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 1:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
VFBGA Assignment
D3, E4, F4, F3, G4, G3,
G1, F1, F2, E2, D2, C2,
C1, B1, G6, F6, F5, E5,
H5, H4, H3, H2, D4,
J4, E3, H6, G2, H1,
C4, C3, B4, B3, A5,
D5, C6, C5, B6
A4, A3
J5, J6
A6
A2
G5
A1
D6
D1
B5
B2
E1
E6
J2
J3
J1
VFBGA Ball Descriptions
Note 1
Notes:
DQ[15:0]
Symbol
A[22:0]
ADV#
WAIT
V
V
WE#
CLK
CRE
OE#
UB#
RFU
CE#
LB#
V
V
CC
SS
CC
SS
1. The CLK and ADV# inputs can be tied to V
Q
Q
nous or page mode. WAIT will be asserted but should be ignored during asynchronous and
page mode operations.
Output
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
—
Address inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address
lines are also used to define the value to be loaded into the BCR or the RCR.
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the
address is latched on the first rising CLK edge when ADV# is active. CLK is
static LOW during asynchronous access READ and WRITE operations and
during PAGE READ ACCESS operations.
Address valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous
READ and WRITE operations. ADV# can be held LOW during asynchronous
READ and WRITE operations.
Control register enable: When CRE is HIGH, WRITE operations load the RCR
or BCR, and READ operations access the RCR, BCR, or DIDR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device
is disabled and goes into standby or deep power-down mode.
Output enable: Enables the output buffers when LOW. When OE# is HIGH,
the output buffers are disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is a WRITE to either a configuration register or to the memory
array.
Lower byte enable. DQ[7:0]
Upper byte enable. DQ[15:8]
Data inputs/outputs.
Wait: Provides data-valid feedback during burst READ and WRITE
operations. The signal is gated by CE#. WAIT is used to arbitrate collisions
between refresh and READ/WRITE operations. WAIT is also asserted at the
end of a row unless wrapping within the burst length. WAIT is asserted and
should be ignored during asynchronous and page mode operations. WAIT is
High-Z when CE# is HIGH.
Reserved for future use.
Device power supply: (1.7–1.95V) Power supply for device core operation.
I/O power supply: (1.7–3.6V) Power supply for input/output buffers.
V
V
SS
SS
Q must be connected to ground.
must be connected to ground.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
SS
if the device is always operating in asynchro-
Description
©2004 Micron Technology, Inc. All rights reserved.