FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 120

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.8.3
5.8.3.1
5.8.3.2
120
Table 5-17. APIC Interrupt Mapping (Sheet 2 of 2)
NOTES:
APIC Bus Functional Description
Physical Characteristics of APIC
The APIC bus is a 3-wire synchronous bus connecting all I/O and local APICs. Two of these wires
are used for data transmission, and one wire is a clock. For bus arbitration, the APIC uses only one
of the data wires. The bus is logically a wire-OR and electrically an open-drain connection
providing for both bus use arbitration and arbitration for lowest priority. The APIC bus speed can
run from 16.67 MHz to 33 MHz.
APIC Bus Arbitration
The I/O APIC uses one wire arbitration to win bus ownership. A rotating priority scheme is used
for APIC bus arbitration. The winner of the arbitration becomes the lowest priority agent and
assumes an arbitration ID of 0. All other agents, except the agent whose arbitration ID is 15,
increment their Arbitration IDs by one. The agent whose ID was 15 will take the winner's
arbitration ID and will increment it by one. Arbitration IDs are changed only for messages that are
transmitted successfully (except for the Low Priority messages). A message is transmitted
successfully if no CS error or acceptance error was reported for that message.
An APIC agent can use two different priority schemes: Normal or EOI. EOI has the highest
priority. EOI priority is used to send EOI messages for level interrupts from a local APIC to an I/O
APIC. When an agent requests the bus with EOI priority, all other agents requesting the bus with
normal priorities will back off.
1. IRQ 14 and 15 can only be driven directly from the pins when in legacy IDE mode.
2. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15 receive
IRQ #
active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt
sources.
13
14
15
16
17
18
19
20
21
22
23
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
SERIRQ
Yes
Yes
N/A
N/A
N/A
N/A
Via
No
Direct from
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
PIRQ[G]#
PIRQ[H]#
PIRQ[E]#
PIRQ[F]#
Yes
Yes
pin
No
1
1
message
Via PCI
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
FERR# logic
USB UHCI Controller #1
AC ’97 Audio, Modem, option for SMbus
USB UHCI Controller #3, Native IDE
USB UHCI Controller #2
LAN, option for SCI, TCO
Option for SCI, TCO
Option for SCI, TCO
USB EHCI Controller, option for SCI, TCO
Intel
Internal Modules
®
82801DBM ICH4-M Datasheet