FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 180

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.15.2.5
180
Warning:
Note: Native Mode IDE/ACPI S3 Resume Hang Avoidance:
In this mode, the ICH4 does not drive the PCI Interrupt associated with this function. That is only
used in native mode.
Native Mode
In this case both the primary and secondary channels share an interrupt. It will be internally
connected to PIRQ[C]# (IRQ18 in APIC mode). The interrupt will be active-low and shared.
Behavioral notes in native mode are:
System BIOS must clear the interrupt bit (Bit 2) in Bus Master IDE Status Register for BOTH
primary and secondary channels prior to passing control to the OS during resume from S3 state
(STR). This ensures that the pending IDE interrupt(s) are cleared when the control is passed to the
OS. The registers are locked in I/O space via BM_BASE register (Bus 0: Device 31: Register 20-
23h) at offset 02h and offset 0Ah, respectively. Failure to do this may result in system hang when
the OS starts executing resume sequence from S3 (STR) under certain conditions. These conditions
include a combination of the following:
- Only a single channel of IDE is enabled (either Primary or Secondary)
- Native IDE Mode capability is reported by the BIOS
- OS is capable of dynamically switching from Legacy IDE Mode to Native IDE Mode.
A system hang may occur if there exists a pending IDE Interrupt status bit during the legacy IDE
Mode to Native IDE mode sequence, the OS software may not clear the IDE interrupt(s), resulting
in an apparent hang condition (interrupt storm).
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following steps are
required:
1. Software prepares a PRD Table in system memory. The PRD Table must be DWord aligned
2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a 1 to the Start bit in the Command
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The IRQ14 and IRQ15 pins do not affect the internal IRQ14 and IRQ15 inputs to the interrupt
controllers. The IDE logic forces these signals inactive in such a way that the Serial IRQ
source may be used.
The IRQ14 and IRQ15 inputs (not external IRQ[14:15] pins) to the interrupt controller can
come from other sources (Serial IRQ, PIRQx).
The IRQ14 and IRQ15 pins are inverted from active-high to the active-low PIRQ.
When switching the IDE controller to native mode, the IDE Interrupt Pin register (see
Section
interrupt is still active when the masking ends, the interrupt will be allowed to be asserted.
and must not cross a 64-KB boundary.
Register. The direction of the data transfer is specified by setting the Read/Write Control bit.
The interrupt bit and Error bit in the Status register are cleared.
Register. The first entry in the PRD table is fetched and loaded into two registers which are not
10.1.19) will be masked. If an interrupt occurs while the masking is in place and the
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82801DBM ICH4-M Datasheet