FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 299

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

8.1.24
Intel
®
82801DBM ICH4-M Datasheet
BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
15:12
Bit
11
10
9
8
7
6
5
4
Reserved
Discard Timer SERR# Enable (DTSE) — R/W. Controls the generation of SERR# on the primary
interface in response to a timer discard on the secondary interface:
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard.
NOTE: This bit replaces bit 1 of offset 90h, which held this function in ICH3.
Discard Timer Status (DTS) — R/WC.
0 = Not Expired. Software clears this bit by writing a 1 to the bit position.
1 = Secondary discard timer expired (there is no discard timer for the primary interface)
NOTE: This bit replaces bit 1 of offset 92h, which had this function in ICH3.
Secondary Discard Timer (SDT) — R/W. Sets the maximum number of PCI clock cycles that the
ICH4 waits for an initiator on PCI to repeat a delayed transaction request. The counter starts once the
delayed transaction completion is at the head of the queue. If the master has not repeated the
transaction at least once before the counter expires, the ICH4 discards the transaction from its queue.
0 = The PCI master timeout value is between 2
1 = The PCI master timeout value is between 2
Primary Discard Timer (PDT ) — R/W. This bit is RW for software compatibility only.
Fast Back to Back Enable — RO. Hardwired to 0. The PCI logic will not generate fast back-to-back
cycles on the PCI bus.
Secondary Bus Reset — RO. Hardwired to 0. The ICH4 does not follow the P2P bridge reset scheme;
Software-controlled resets are implemented in the PCI-LPC device.
Master Abort Mode — R/W. This bit controls the behavior of the ICH4 when a master abort occurs
on a transaction that crosses the hub interface-PCI bridge in either direction. The default is 0.
0 = ICH4 behaves in the following manner:
1 = ICH4 treats the master abort as an error:
VGA 16-Bit Decode. This bit does not have any functionality relative to address decodes because
the ICH4 will forward the cycles to PCI, independent of the decode. Writes of 1 have no impact other
than to force the bit to 1. Writes of 0 have no impact other than to force the bit to 0. Reads to this bit
will return the previously written value (or 0 if no writes since reset).
• Hub Interface Completion-Required requests to PCI: when these master abort on PCI, the ICH4
• Hub Interface Posted Writes to PCI: when these master abort on PCI, the ICH4 discards the data.
• PCI Reads to Hub Interface: when these master abort on Hub Interface, the ICH4 returns the
• PCI writes to Hub Interface: the ICH4 has no idea when these “master-abort.”
• Hub Interface Completion-Required requests to PCI: when these master abort on PCI, the ICH4
• Hub Interface Posted Writes to PCI: when these master abort on PCI, the ICH4 discards the data
• PCI Reads to Hub Interface: when these master abort on Hub Interface, the ICH4 terminates the
• PCI writes to Hub Interface: the ICH4 has no idea when these “master-abort.”
returns a master abort status. For reads, FFFFh is returned for each DWORD.
data provided with the Hub Interface master abort packet to the PCI requestor.
returns a target abort status. For reads, FFFFh is returned for each DWORD.
and sets the Primary Signaled SERR# bit (if the corresponding SERR_EN bit is set).
cycle with a target abort and flushes the remainder of the prefetched data.
3E–3Fh
0000h
Hub Interface to PCI Bridge Registers (D30:F0)
Description
15
10
Attribute:
Size:
and 2
and 2
16
11
PCI clocks
PCI clocks
R/W, R/WC, RO
16 bits
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