FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 478

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
13.2
13.2.1
478
Table 13-2. SMB I/O Registers
SMBUS I/O Registers
HST_STS—Host Status Register
Register Offset:
Default Value:
All status bits are set by hardware and cleared by the software writing a one to the particular bit
position. Writing a zero to any bit position has no effect.
Offset
0Ah
0Ch
0Dh
0Eh
0Fh
Bit
00h
02h
03h
04h
05h
06h
07h
08h
09h
10h
11h
14h
16h
17h
7
Byte Done Status (DS) — R/WC. This bit will be set to 1 when the host controller has received a
byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write
commands) when the 32-byte buffer is not being used. Note that this bit will be set, even on the last
byte of the transfer. Software clears the bit by writing a 1 to the bit position. This bit is not set when
transmission is due to the D110 interface heartbeat.
This bit has no meaning for block transfers when the 32-byte buffer is enabled.
NOTE: When the last byte of a block message is received, the host controller will set this bit.
HOST_BLOCK_DB
SMLINK_PIN_CTL
SMBUS_PIN_CTL
NOTIFY_DADDR
NOTIFY_DHIGH
NOTIFY_DLOW
XMIT_SLVA
RCV_SLVA
Mnemonic
HST_CMD
SLV_DATA
SLV_CMD
HST_STS
HST_CNT
AUX_STS
AUX_CTL
SLV_STS
HST_D0
HST_D1
However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt
handler clears the BYTE_DONE_STS bit, the message is considered complete, and the
host controller will then set the INTR bit (and generate another interrupt). Thus, for a block
message of n bytes, the Intel ICH4 will generate n+1 interrupts. The interrupt handler needs
to be implemented to handle these cases.
PEC
00h
00h
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Host Block Data Byte
Packet Error Check
Receive Slave Address
Slave Data
Auxiliary Status
Auxiliary Control
SMLink Pin Control
SMBus Pin Control
Slave Status
Slave Command
Notify Device Address
Notify Data Low Byte
Notify Data High Byte
Register Name
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/WC, RO
8-bits
Default
0000h
00h
00h
00h
00h
00h
00h
00h
00h
44h
00h
00h
04h
04h
00h
00h
00h
00h
00h
R/W, WO
R/W, RO
R/W, RO
R/WC,
R/WC
R/WC
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO