FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 341

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.4.2
9.4.3
Intel
®
82801DBM ICH4-M Datasheet
ICW2—Initialization Command Word 2 Register
Offset Address:
Default Value:
ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt
vector address. The value programmed for bits[7:3] is used by the CPU to define the base address
in the interrupt vector table for the interrupt routines associated with each IRQ on the controller.
Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller.
ICW3—Master Controller Initialization Command Word 3
Register
Offset Address:
Default Value:
7:3
1:0
Bit
2
7:3
2:0
Bit
0 = These bits must be programmed to zero.
Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the slave controller is
cascaded on IRQ2. When IRQ8#
resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through the master
controller’s priority solver. If it wins, the INTR signal is asserted to the CPU, and the returning interrupt
acknowledge returns the interrupt vector for the slave controller.
1 = This bit must always be programmed to a 1.
0 = These bits must be programmed to zero.
Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the interrupt vector
table for the interrupt routines associated with each interrupt request level input.
Interrupt Request Level — WO. When writing ICW2, these bits should all be 0. During an
interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the
interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the
data bus during the second INTA# cycle. The code is a three bit binary code:
CodeMaster InterruptSlave Interrupt
000IRQ0IRQ8
001IRQ1IRQ9
010IRQ2IRQ10
011IRQ3IRQ11
100IRQ4IRQ12
101IRQ5IRQ13
110IRQ6IRQ14
111IRQ7IRQ15
Master Controller
Slave Controller
All bits undefined
21h
All bits undefined
–
0A1h
–
–
021h
IRQ15 is asserted, it goes through the slave controller’s priority
Description
Description
Attribute:
Size:
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
WO
8 bit /controller
WO
8 bits
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