FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 555

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FW82801DBM S L6DN

Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801DBM S L6DN

Lead Free Status / RoHS Status
Not Compliant
Intel
®
Table 17-12. Ultra ATA Timing (Mode 3, Mode 4, Mode 5)
82801DBM ICH4-M Datasheet
Sym
t83b
t84b
t85b
t86b
t92a
t80
t81
t82
t83
t84
t85
t86
t87
t88
t89
t90
t91
Sustained Cycle Time
(T2cyctyp)
Cycle Time (Tcyc)
Two Cycle Time (T2cyc)
Data Setup Time (Tds)
Recipient IC data setup time
(from data valid until
STROBE edge)
(see Note 2) (Tdsic)
Data Hold Time (Tdh)
Recipient IC data hold time
(from STROBE edge until
data may become invalid)
(see Note 2) (Tdhic)
Data Valid Setup Time
(Tdvs)
Sender IC data valid setup
time (from data valid until
STROBE edge) (see Note 2)
(Tdvsic)
Data Valid Hold Time (Tdvh)
Sender IC data valid hold
time (from STROBE edge
until data may become
invalid) (see Note 2) (Tdvhic)
Limited Interlock Time (Tli)
Interlock Time w/ Minimum
(Tmli)
Envelope Time (Tenv)
Ready to Pause Time (Trp)
DMACK setup/hold Time
(Tack)
CRC Word Setup Time at
Host (Tcvs)
Parameter (1)
Mode 3 (ns) Mode 4 (ns) Mode 5 (ns)
22.6
Min
100
6.8
4.8
6.2
9.0
39
86
20
20
20
20
20
7
5
0
90
Max
100
55
Min
100
4.8
4.8
6.7
9.5
6.2
9.0
6.7
25
57
20
20
20
5
5
0
60
Max
100
55
16.8
Min
4.0
2.3
4.6
2.8
4.8
6.0
4.8
6.0
38
20
20
85
20
10
0
40
Max
75
50
Electrical Characteristics
Sender
Connector
End
Recipient
Connector
Sender
Connector
Recipient
Connector
ICH4 Balls
Recipient
Connector
ICH4 Balls
Sender
Connector
ICH4 Balls
Sender
Connector
ICH4 Balls
See Note 2
Host
Connector
Host
Connector
Recipient
Connector
Host
Connector
Host
Connector
Measuring
Location
Figure
17-11
Figure
17-11
Figure
17-11
Figure
17-11
Figure
17-11
Figure
17-11
Figure
17-13
Figure
17-13
Figure
17-10
Figure
17-12
Figure
17-10,
Figure
17-13
Figure
555

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