FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 255

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.19.6
Intel
®
Table 5-103. AC-link State during PCIRST#
82801DBM ICH4-M Datasheet
System Reset
Table 5-103
NOTES:
The transition of AC_RST# to the deasserted state will only occur under driver control. In the
S1-M sleep state, the state of the AC_RST# signal is controlled by the AC ’97 Cold Reset# bit (bit
1) in the Global Control register. AC_RST# will be asserted (low) by the ICH4 under the following
conditions:
Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically.
Only software can deassert the Cold Reset# bit, and hence the AC_RST# signal. This bit, while it
resides in the core well, will remain cleared upon return from S3/S4/S5 sleep states. The AC_RST#
pin will remain actively driven from the resume well as indicated.
1. ICH4 core well outputs are used as strapping options for the ICH4, sampled during system reset. These
2. The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC ’97 Global
3. AC_RST# will be held low during S3–S5. It cannot be programmed high during a suspend state.
4. AC_BIT_CLK and AC_SDIN[2:0] are driven low by the codecs during normal states. If the codec is powered
AC_RST#
AC_SDOUT
AC_SYNC
AC_BIT_CLK
AC_SDIN[2:0]
•
•
•
•
•
signals may have weak pullups/pulldowns on them. The ICH4 outputs will be driven to the appropriate level
prior to AC_RST# being deasserted, preventing a codec from entering test mode. Straps are tied to the core
well to prevent leakage during a suspend state.
Control Register is set to 1. All other times, the pull-down resistor is disabled.
during suspend states it will hold these signals low. However, if the codec is not present, or not powered in
suspend, external pull-down resistors are required.
Signal
RSMRST# (system reset, including the a reset of the resume well and PCIRST#)
Mechanical power up (causes PCIRST#)
Write to CF9h hard reset (causes PCIRST#)
Transition to S3/S4/S5 sleep states (causes PCIRST#)
Write to AC ’97 Cold Reset# bit in the Global Control Register.
indicates the states of the link during various system reset and sleep conditions.
Resume
Core
Core
Core
Resume
Power
Plane
1
3
Output
Output
Output
Input
Input
I/O
Driven by codec
Driven by codec
PCIRST#/
During
Low
Low
Low
PCIRST#/
Running
Running
Running
Running
After
Low
Cold Reset
bit (Hi)
Low
Low
S1-M
Low
Low
2,4
2,4
Functional Description
Low
Low
Low
Low
Low
S3
2,4
2,4
Low
Low
S4/S5
Low
Low
Low
2,4
2,4
255