FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 53

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 2-10. Power Management Interface Signals (Sheet 2 of 2)
82801DBM ICH4-M Datasheet
C3_STAT#
SUSCLK
STP_PCI#
STP_CPU#
BATLOW#
CPUPERF#
SSMUXSEL
VGATE
/ VRMPWRGD
DPRSLPVR
AGPBUSY#
Name
Type
OD
O
O
O
O
O
O
I
I
I
C3_STAT#: This signal will typically be configured as C3_STAT#. It is used for
indicating to an AGP device that a C3 state transition is beginning or ending. If
C3_STAT# functionality is not required, this signal may be used as a GPO.
NOTE: This signal will be asserted in S1-M on the ICH4-M.
Suspend Clock: Output of the RTC generator circuit to use by other chips for
refresh clock.
AGP Bus Busy: To support the C3 state. This signal is an indication that the
AGP device is busy. When this signal is asserted, the BM_STS bit will be set. If
this functionality is not needed, this signal may be configured as a GPI.
Stop PCI Clock: This signal is an output to the external clock generator for it to
turn off the PCI clock. Used to support PCI CLKRUN# protocol. If this
functionality is not needed, This signal can be configured as a GPO.
Stop CPU Clock: Output to the external clock generator for it to turn off the
processor clock. Used to support the C3 state. If this functionality is not needed,
this signal can be configured as a GPO.
Battery Low: This signal is an input from the battery to indicate that there is
insufficient power to boot the system. Assertion will prevent wake from S1-M–S5
state. Can also be enabled to cause an SMI# when asserted.
CPU Performance: CPUPERF# is used for Intel SpeedStep technology
support. The signal selects which power state to put the processor in.
SpeedStep Mux Select: SSMUXSEL is used for Intel SpeedStep technology
support. The signal selects the voltage level for the processor.
VGATE/VRM Power Good: VGATE/VRMPWRGD is used for Intel SpeedStep
technology support. This is an output from the processor’s voltage regulator to
indicate that the voltage is stable. This signal may go inactive during an Intel
SpeedStep transition.
Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of
VRM during C4 and S1-M states. When the signal is high, the voltage regulator
outputs the lower “Deeper Sleep” voltage. When the signal is low (default), the
voltage regulator outputs the higher “Normal” voltage. During PCIRST#, the
output driver is disabled and an internal pull-down is enabled. This is needed for
implementing a strap on the pin. When PCIRST# deasserts, the output driver is
enabled. To guarantee no glitches on the DPRSLPVR pin, the pull-down is
disabled after the output driver is fully enabled.
NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a functional
strap. See
Section 2.20.1
Description
for more details.
Signal Description
53