FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 435

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

11.2.7
Intel
®
82801DBM ICH4-M Datasheet
Note: For Function 0, this register applies to ICH4 USB ports 0 and 1; for Function 1, this register applies
PORTSC[0,1]—Port Status and Control Register
I/O Offset:
Default Value:
to ICH4 USB ports 2 and 3; for Function 2, this register applies to ICH4 USB ports 4 and 5.
After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a port are: no
device connected, port disabled, and the bus line status is 00 (single-ended zero).
15:13
Bit
12
11
10
9
8
7
6
Reserved — RO.
Suspend — R/W . This bit should not be written to a 1 if global suspend is active (bit 3=1 in the
USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows:
When in suspend state, downstream propagation of data is blocked on this port, except for single-
ended 0 resets (global reset and port reset). The blocking occurs at the end of the current
transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the
port is sensitive to resume detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is a transaction currently in
progress on the USB.
0 = Port not in suspend state.
1 = Port in suspend state.
NOTE: Normally, if a transaction is in progress when this bit is set, the port will be suspended
Over-current Indicator — R/WC. Set by hardware.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Overcurrent pin has gone from inactive to active on this port.
Over-current Active — RO. This bit is set and cleared by hardware.
0 = Indicates that the overcurrent pin is inactive (high).
1 = Indicates that the overcurrent pin is active (low).
Port Reset — R/W .
0 = Port is not in Reset.
1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling.
Low Speed Device Attached (LS) — RO . Writes have no effect.
0 = Full speed device is attached.
1 = Low speed device is attached to this port.
Reserved — RO. Always read as 1.
Resume Detect (RSM_DET) — R/W. Software sets this bit to a 1 to drive resume signaling. The
Host Controller sets this bit to a 1 if a J-to-K transition is detected for at least 32 microseconds while
the port is in the Suspend state. The ICH4 will then reflect the K-state back onto the bus as long as
the bit remains a 1, and the port is still in the suspend state (bit 12,2 are 11). Writing a 0 (from 1)
causes the port to send a low speed EOP. This bit will remain a 1 until the EOP has completed.
0 = No resume (K-state) detected/driven on port.
1 = Resume detected/driven on port.
Bits [12,2]Hub State
X0Disable
01Enable
11Suspend
when the current transaction completes. However, in the case of a specific error condition
(out transaction with babble), the ICH4 may issue a start-of-frame, and then suspend the
port.
Port 0/2/4: Base + (10
Port 1/3/5: Base + (12
0080h
–
–
11h)Attribute:
13h)
Description
Size:
USB UHCI Controllers Registers
R/WC, RO, R/W (Word writes only)
16 bits
435