FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 476

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
13.1.7
13.1.8
13.1.9
13.1.10
476
BCC—Base Class Code Register (SMBUS—D31:F3)
Address Offset:
Default Value:
SMB_BASE—SMBUS Base Address Register
(SMBUS—D31:F3)
Address Offset:
Default Value:
SVID — Subsystem Vendor ID (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
SID — Subsystem ID (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
31:16
15:0
15:0
15:5
4:1
Bit
Bit
Bit
Bit
7:0
0
Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the Subsystem ID
(SID) register, enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS into the
IDE_SVID register.
Subsystem ID (SID) — R/Write-Once. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. The value returned
by reads to this register is the same as that which was written by BIOS into the IDE_SID register.
Reserved — RO
Base Address — R/W. Provides the 32-byte system I/O base address for the ICH4 SMB logic.
Reserved — RO
I/O Space Indicator — RO. This read-only bit is always 1, indicating that the SMB logic is I/O
mapped.
Base Class Code — RO.
0Ch = Serial controller.
20–23h
2Ch–2Dh
00h
2Eh–2Fh
00h
0Bh
0Ch
00000001h
No
No
Description
Description
Description
Description
Attributes:
Size:
Attribute:
Size:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
RO
8 bits
R/W, RO
32-bits
RO
16 bits
Core
RO
16 bits
Core