FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 442
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FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
Lead Free Status / RoHS Status
Not Compliant
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EHCI Controller Registers (D29:F7)
12.1.10
12.1.11
12.1.12
442
MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Reset:
SID—USB EHCI Subsystem ID Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Reset:
31:10
15:0
15:0
9:4
2:1
Bit
Bit
Bit
3
0
Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10], respectively.
This provides 1 kB of locatable memory space aligned to 1-kB boundaries.
Reserved
Prefetchable — RO. Hardwired to 0; indicates that this range should not be prefetched.
Type — RO. Hardwired to 00b; indicates that this range can be mapped anywhere within 32-bit
address space.
Resource Type Indicator (RTE) — RO. Hardwired to 0; indicates that the base address field in this
register maps to memory space.
Subsystem Vendor ID (SVID) — R/W-Special. This register, in combination with the USB EHCI
Subsystem ID register, enables the operating system to distinguish each subsystem from the others.
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (offset 80h, bit 0) is set to 1.
Subsystem ID (SID) — R/W-Special. BIOS sets the value in this register to identify the Subsystem
ID. This register, in combination with the Subsystem Vendor ID register, enables the operating
system to distinguish each subsystem from other(s).
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (offset 80h, bit 0) is set to 1.
00000000h
None
None
10
2C
XXXXh
2E
XXXXh
–
–
–
13h
2Fh
2Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
R/W, RO
32 bits
R/W-Special
16 bits
R/W-Special
16 bits
®
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