FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 516

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Modem Controller Registers (D31:F6)
15.1.1
15.1.2
15.1.3
516
VID—Vendor Identification Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
DID—Device Identification Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
PCICMD—PCI Command Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete details on each
bit.
15:10
15:0
15:0
Bit
Bit
Bit
9
8
7
6
5
4
3
2
1
0
Vendor Identification Value — RO.
Device Identification Value — RO.
Reserved. Read 0.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SEN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. Controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — RO. Hardwired to 0; AC ‘97 does not respond to memory
accesses.
I/O Space Enable (IOSE) —R /W. This bit controls access to the I/O space registers.
0 = Disable access. (default = 0).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
0000h
00
8086
No
02
24C6h
No
04
No
–
–
–
01h
03h
05h
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
RO
16 Bits
Core
RO
16 Bits
Core
R/W, RO
16 bits
Core