NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 310
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 310 of 890
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Table 104.
8.1.1
8.1.2
310
Gigabit LAN Configuration Registers Address Map
(Gigabit LAN —D25:F0) (Sheet 2 of 2)
VID—Vendor Identification Register
(Gigabit LAN—D25:F0)
Address Offset: 00h
Default Value:
DID—Device Identification Register
(Gigabit LAN—D25:F0)
Address Offset: 02h–03h
Default Value:
DCh–DDh
D0h–D1h
D2h–D3h
D4h–D7h
D8h–DBh
15:0
15:0
Bit
Offset
Bit
CFh
Device ID — RO. This is a 16-bit value assigned to the Intel
controller. The field may be auto-loaded from the NVM word 0Dh during initialization
time depending on the "Load Vendor/Device ID" bit field in NVM word 0Ah.
Vendor ID — RO. This is a 16-bit value assigned to Intel. The field may be auto-loaded
from the NVM at address 0Eh during init time depending on the "Load Vendor/Device
ID" bit field in NVM word 0Ah with a default value of 8086h.
Mnemonic
MADDH
CLIST2
MADDL
MDAT
MCTL
DR
8086h
See bit description
–
01h
Data Register
Capabilities List 2
Message Control
Message Address Low
Message Address High
Message Data
Register Name
Description
Description
Attribute:
Size:
Attribute:
Size:
Gigabit LAN Configuration Registers
See register
See register
See register
See register
Function 0
description
description
description
description
®
Default
RO
16 bits
RO
16 bits
0005h
0080h
ICH8 Gigabit LAN
Intel
®
ICH8 Family Datasheet
R/W, RO
Type
R/W
R/W
R/W
RO
RO
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