NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 528
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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528
21:8
Bit
23
22
7
6
5
4
3
2
1
0
Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and
PxIS.IPMS are set, the ICH8 will generate an interrupt.
NOTE: Should be written as 0. Port Multiplier not supported by ICH8.
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and
PxIS.PRCS is set, the ICH8 shall generate an interrupt.
Reserved - Should be written as 0
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH8 will
generate an interrupt.
For systems that do not support an interlock switch, this bit shall be a read-only 0.
Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS
are set, the ICH8 will generate an interrupt.
Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and
PxS.DPS are set, the ICH8 will generate an interrupt
Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an
unknown FIS is received, the ICH8 will generate this interrupt.
Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and
PxS.SDBS are set, the ICH8 will generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS
are set, the ICH8 will generate an interrupt.
PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS
are set, the ICH8 will generate an interrupt.
Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and
GHC.IE and PxS.DHRS are set, the ICH8 will generate an interrupt.
Description
SATA Controller Registers (D31:F2)
Intel
®
ICH8 Family Datasheet
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