NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 391
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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LPC Interface Bridge Registers (D31:F0)
9.8.3
Note:
Table 115.
Intel
10hh–13h
®
PMBASE
+ Offset
3Dh–41h
00h–01h
02h–03h
04h–07h
08h–0Bh
0Ch–0Fh
15h–16h
17h–18h
28h–2Bh
2Ch–2Fh
30h–33h
34h–37h
38h–39h
3Ah–3Bh
44h–45h
51h–53h
46h–4Fh
ICH8 Family Datasheet
14h
15h
16h
17h
18h
19h
20h
20h
42h
43h
50h
50h
ALT_GP_SMI_STS
Power Management I/O Registers
Table 115
support. These registers are enabled in the PCI Device 31: Function 0 space
(PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers
are defined to support the ACPI 2.0 specification, and use the same bit names.
All reserved bits and registers will always return 0 when read, and will have no effect
when written.
ACPI and Legacy I/O Register Map (Sheet 1 of 2)
ALT_GP_SMI_EN
DEVACT_STS
Mnemonic
PROC_CNT
GPE_CNTL
GPE0_STS
PM1_TMR
PM1_STS
PM1_CNT
PM2_CNT
GPE0_EN
SMI_STS
PM1_EN
SS_CNT
SMI_EN
LV2
LV3
LV4
LV5
LV6
—
—
—
—
—
—
—
—
—
—
shows the registers associated with ACPI and Legacy power management
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Reserved
Processor Control
Level 2 (Mobile Only)
Reserved (Desktop Only)
Level 3 (Mobile Only)
Level 4 (Mobile Only)
Reserved (Desktop Only)
Level 5 (Mobile Only)
Level 6 (Mobile Only)
Reserved
Reserved (Desktop Only)
PM2 Control (Mobile Only)
General Purpose Event 0
Status
General Purpose Event 0
Enables
SMI# Control and Enable
SMI Status
Alternate GPI SMI Enable
Alternate GPI SMI Status
Reserved
General Purpose Event
Control
Reserved
Device Activity Status
Reserved
Reserved (Desktop Only)
Intel SpeedStep
Technology Control
(Mobile Only)
Reserved
Register Name
®
PM1a_EVT_BLK+2
PM1a_CNT_BLK
PM2a_CNT_BLK
PM1a_EVT_BLK
ACPI Pointer
GPE0_BLK+4
PMTMR_BLK
GPE0_BLK
P_BLK+4
P_BLK+5
P_BLK+6
P_BLK+7
P_BLK+8
P_BLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
00000000h
xx000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Default
0000h
0000h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
01h
—
—
—
—
—
—
—
—
—
—
R/W (special)
R/W (special)
R/W, RO, WO
R/WC, RO
R/W, WO,
R/W, WO
RO, R/W
R/WC
Type
R/WC
R/WC
R/WC
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
—
—
—
—
—
—
—
—
—
—
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