NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 736
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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18.1.60
18.1.61
736
CEM — Correctable Error Mask Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 154h
Default Value:
When set, the corresponding error in the CES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
AECC — Advanced Error Capabilities and Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 158h
Default Value:
31:14
11:9
31:9
5:1
4:0
Bit
Bit
13
12
8
7
6
0
8
7
6
5
Reserved
Advisory Non-Fatal Error Mask (ANFEM) — R/WO.
0 = Does not mask Advisory Non-Fatal errors.
1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control
This register is set by default to enable compatibility with software that does not
comprehend Role-Based Error Reporting.
Replay Timer Timeout Mask (RTT) — R/WO. Mask for replay timer timeout.
Reserved
Replay Number Rollover Mask (RNR) — R/WO. Mask for replay number rollover.
Bad DLLP Mask (BD) — R/WO. Mask for bad DLLP reception.
Bad TLP Mask (BT) — R/WO. Mask for bad TLP reception.
Reserved
Receiver Error Mask (RE) — R/WO. Mask for receiver errors.
Reserved
ECRC Check Enable (ECE) — RO. ECRC is not supported.
ECRC Check Capable (ECC) — RO. ECRC is not supported.
ECRC Generation Enable (EGE) — RO. ECRC is not supported.
ECRC Generation Capable (EGC) — RO. ECRC is not supported.
First Error Pointer (FEP) — RO.
register and (b) updating the Uncorrectable Error Status register.
00000000h
00000000h
–
–
157h
15Bh
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI Express* Configuration Registers
R/WO
32 bits
RO
32 bits
Intel
®
ICH8 Family Datasheet
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