NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 716
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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18.1.30
716
LSTS—Link Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 52h–53h
Default Value:
11
10
9:4
3:0
15:14
Bit
13
12
Reserved
Data Link Layer Active (DLLA) — RO. Default value is 0b.
0 = Data Link Control and Management State Machine is not in the DL_Active state
1 = Data Link Control and Management State Machine is in the DL_Active state
Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel
the same reference clock as on the platform and does not generate its own clock.
Link Training (LT) — RO. Default value is 0b.
0 = Link training completed.
1 = Link training is occurring.
Link Training Error (LTE) — RO. Not supported. Set value is 0b.
Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the
given PCI Express* link. The contents of this NLW field is undefined if the link has not
successfully trained.
NOTE: 000001b = x1 link width, 000010b =x2 linkwidth (not supported), 000100b =
Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI
Express* link.
01h = Link is 2.5 Gb/s.
Port #
1
2
3
4
5
6
x4 linkwidth
See bit description
000001b, 000010b,
000100b
000001b
000001b
000001b
000001b, 000010b
000001b
Possible Values
Description
Attribute:
Size:
PCI Express* Configuration Registers
RO
16 bits
Intel
®
ICH8 Family Datasheet
®
ICH8 uses
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