NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 764

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

20.2.1.3
20.2.1.4
764
FLMAP1—Flash Map 1 Register
(Flash Descriptor Memory Mapped Configuration Registers)
Memory Address:FDBAR + 008h
FLMAP2—Flash Map 2 Register
(Flash Descriptor Memory Mapped Configuration Registers)
Memory Address:FDBAR + 00Ch
31:24
23:16
15:11
10:8
7:0
31:16
15:8
7:0
Bits
Bits
Reserved
MCH Strap Length (MSL): This field identifies the 1s based number of DWords of MCH
Straps to be read, up to 255 DWs (1 KB) maximum. A setting of all 0s indicates there
are no MCH DW straps.
Flash MCH Strap Base Address (FMSBA): This identifies address bits [11:4] for the
MCH Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
For validation purposes, the recommended FMSBA is: 20h
ICH8 Strap Length (ISL): This field identifies the 1’s based number of DWords of
ICH8 Straps to be read, up to 255 DWs (1 KB) maximum. A setting of all 0s indicates
there are no ICH8 DW straps.
Flash ICH8 Strap Base Address (FISBA): This field identifies address bits [11:4] for
the ICH8 Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
For validation purposes, the recommended FISBA is: 10h
Reserved
Number Of Masters (NM): This field identifies the total number of Flash Regions. This
number is 0’s based.
Flash Master Base Address (FMBA): This identifies address bits [11:4] for the
Master portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
For validation purposes, the recommended FMBA is: 06h
Description
Description
Size:
Size:
Serial Peripheral Interface (SPI)
32 bits
32 bits
Intel
®
ICH8 Family Datasheet