NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 783
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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Serial Peripheral Interface (SPI)
20.3.9
20.3.10
Intel
®
ICH8 Family Datasheet
FREG2—Flash Region 2 (ME) Register
(
Memory Address:GLBAR + 5Ch
Default Value:
FREG3—Flash Region 3 (GbE) Register
(
Memory Address:GLBAR + 60h
Default Value:
31:29
28:16
15:13
12:0
31:29
28:16
15:13
12:0
GbE LAN Memory Mapped Configuration Registers
GbE LAN Memory Mapped Configuration Registers
Bit
Bit
Reserved
Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 2
Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
Reserved
Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 2
Base.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base.
Reserved
Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 3
Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Limit
Reserved
Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 3
Base.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Base.
00000000h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
32 bits
RO
32 bits
)
)
783
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