NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 656
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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17.1.28
17.1.29
17.1.30
17.1.31
656
MMLA—MSI Message Lower Address Register
(Intel
Address Offset: 64h-67h
Default Value:
MMUA—MSI Message Upper Address Register
(Intel
Address Offset: 68h-6Bh
Default Value:
MMD—MSI Message Data Register
(Intel
Address Offset: 6Ch-6Dh
Default Value:
PXID—PCI Express* Capability ID Register
(Intel
Address Offset: 70h-71h
Default Value:
31:2
31:0
15:0
15:8
1:0
7:0
Bit
Bit
Bit
Bit
Message Lower Address (MLA) — R/W. Lower address used for MSI message.
Reserved.
Message Upper Address (MUA) — R/W. Upper 32-bits of address used for MSI
message.
Message Data (MD) — R/W. Data used for MSI message.
Next Capability (Next) — RO. Hardwired to 0. Indicates that this is the last capability
structure in the list.
Cap ID (CAP) — RO. Hardwired to 10h. Indicates that this pointer is a PCI Express*
capability structure
®
®
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
00000000h
00000000h
0000h
0010h
Intel
®
Description
Description
Description
Description
High Definition Audio Controller Registers (D27:F0)
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO, R/W
32 bits
R/W
32 bits
R/W
16 bits
RO
16 bits
Intel
®
ICH8 Family Datasheet
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