NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 629
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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SMBus Controller Registers (D31:F3)
16.1.10
16.1.11
16.1.12
Intel
®
ICH8 Family Datasheet
SMB_BASE—SMBUS Base Address Register
(SMBUS—D31:F3)
Address Offset: 20
Default Value:
SVID — Subsystem Vendor Identification Register
(SMBUS—D31:F2/F4)
Address Offset: 2Ch
Default Value:
Lockable:
SID — Subsystem Identification Register
(SMBUS—D31:F2/F4)
Address Offset: 2Eh
Default Value:
Lockable:
31:16
15:5
15:0
15:0
4:1
Bit
Bit
Bit
0
Reserved — RO
Base Address — R/W. This field provides the 32-byte system I/O base address for the
ICH8 SMB logic.
Reserved — RO
IO Space Indicator — RO. Hardwired to 1 indicating that the SMB logic is I/O mapped.
Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the
Subsystem ID (SID) register, enables the operating system (OS) to distinguish
subsystems from each other. The value returned by reads to this register is the same as
that which was written by BIOS into the IDE SVID register.
NOTE: Software can write to this register only once per core well reset. Writes should
Subsystem ID (SID) — RO. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS
into the IDE SID register.
NOTE: Software can write to this register only once per core well reset. Writes should
be done as a single 16-bit cycle.
be done as a single 16-bit cycle.
00000001h
0000h
No
00h
No
–
23h
–
–
2Fh
2Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W, RO
32-bits
RO
16 bits
Core
R/WO
16 bits
Core
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