NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 595

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7, D26:F7)
15.1.20
15.1.21
15.1.22
15.1.23
Intel
®
ICH8 Family Datasheet
DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 58h
Default Value:
NXT_PTR2—Next Item Pointer #2 Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 59h
Default Value:
DEBUG_BASE—Debug Port Base Offset Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 5Ah
Default Value:
USB_RELNUM—USB Release Number Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 60h
Default Value:
15:13
12:0
7:0
7:0
Bit
Bit
7:0
Bit
Bit
Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a
Debug Port Capability structure.
Next Item Pointer 2 Capability — RO. Hardwired to 00h to indicate there are no more
capability structures in this function.
BAR Number — RO. Hardwired to 001b to indicate the memory BAR begins at offset
10h in the EHCI configuration space.
Debug Port Offset — RO. Hardwired to 0A0h to indicate that the Debug Port registers
begin at offset A0h in the EHCI memory range.
USB Release Number — RO. A value of 20h indicates that this controller follows
Universal Serial Bus (USB) Specification, Revision 2.0.
0Ah
00h
20A0h
20h
–
5Bh
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
RO
16 bits
RO
8 bits
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