NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 601
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 601 of 890
- Download datasheet (7Mb)
EHCI Controller Registers (D29:F7, D26:F7)
15.1.29
Intel
®
ICH8 Family Datasheet
ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F7, D26:F7)
Address Offset:
Default Value:
7:1
Bit
0
Bit
3
2
1
0
Reserved
WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally read-
only registers in the EHC function to be written by software. Registers that may only be
written when this mode is entered are noted in the summary tables and detailed
description as “Read/Write-Special”. The registers fall into two categories:
1.
2.
SMI on Periodic Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller
SMI on CF Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will
SMI on HCHalted Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host
SMI on HCReset Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller
System-configured parameters, and
Status bits
80h
00h
will issue an SMI.
issue an SMI.
controller will issue an SMI.
will issue an SMI.
Description
Description
Attribute:
Size:
R/W
8 bits
601
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