AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 106

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
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13
12:10
9:8
7
6
5
4
3
2
1
0
Link Three-State Enable [LDT3SEN]. Read-Write.
0 = During the LDTSTOP_L disconnect sequence the link transmitter signals are driven but in an
1 = During the LDTSTOP_L disconnect sequence, the link transmitter signals are placed into the high
Note: This bit is cleared by PWROK reset but not by LDTRESET_L. AMD recommends that this bit be set high in
Reserved.
CRC Error [CRCERR]. Read. Set by hardware. Write 1 to clear.
1 = Hardware detected a CRC error on the incoming link. Bit[9] applies to the upper byte of the link
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Transmitter Off [TXOFF]. Read. Write 1 only.
1 = No output signals on the link toggle. The input link receivers are disabled and the pins may float.
End Of Chain [ENDOCH]. Read. Write 1 only or set by hardware.
1 = The link is not part of the logical HyperTransport™ chain. Packets issued or forwarded to this
Initialization Complete [INITCPLT]. Read Only. This bit is set by hardware when low-level
HyperTransport™ link initialization has successfully completed. If there is no device on the other end
of the HyperTransport link, or if the device on the other side of the HyperTransport link is unable to
properly perform HyperTransport link initialization, then the bit is not set.
Note: This bit is cleared when LDTRESET_L is asserted; it is not cleared when LDTSTOP_L is asserted.
Link Failure [LKFAIL]. Read. Set by hardware. Write 1 to clear. This bit is set high by hardware when
an error is detected on the link that causes the AMD-8132 tunnel to issue sync flood or if the
HyperTransport™ link is not used in the system.
Note: This bit is cleared by PWROK reset, not by LDTRESET_L.
CRC Error Command [CRCERRCMD]. Read-Write. This bit is intended to be used to check the CRC
failure detection logic of the device on the other side of the link.
0 = Transmitted CRC values match the values calculated per the link specification.
1 = The HyperTransport™ link transmission logic generates erroneous CRC values.
Reserved. CRC test mode is not supported.
CRC Flood Enable [CRCFEN]. Read-Write.
0 = CRC errors do not result in sync packets or setting the LKFAIL bit.
1 = If DevA:0x04[SERREN] is also enabled, CRC errors (in HyperTransport™ link 0 for
Reserved.
undefined state, and the link receiver signals are assumed to be driven.
impedance state and the receivers are prepared for the high impedance mode. For the receivers,
this includes cutting power to the receiver differential amplifiers and ensuring that there are no
resultant high-current paths in the circuits.
and bit[8] applies to the lower byte.
HyperTransport link are either dropped or result in an NXA error response. Packets received from
this HyperTransport link are ignored and CRC is not checked. If the transmitter is still enabled
(TXOFF not asserted), then it drives only NOP packets with good CRC. ENDOCH can be set by
writing a 1 to it or it may be set by hardware if the HyperTransport link is determined to be
disconnected at the rising edge of LDTRESET_L during a cold reset.
DevA:0xC4[CRCFEN]; in HyperTransport link 1 for DevA:0xC8[CRCFEN]) result in sync packets
to both outgoing HyperTransport links and the LKFAIL bit is set.
single-processor systems and be set low in multi-processor systems.
®
2.0 Tunnel Data Sheet
Registers
26792 Rev. 3.07 July 2005
Chapter 3