AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 84

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
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CLEARPCILOG_L. Read-Write.
The purpose of this bit is to prevent the above log bits from causing unexpected sync flooding or fatal/
nonfatal interrupt assertion in a system that only understands standard PCI-to-PCI bridge error
reporting and doesn't query or clear these log bits following a warm reset. When this bit is in its default
state, the log bits pulse and potentially cause sync flooding or fatal/nonfatal interrupts when the error
initially happens, but there will be no leftover state. To preserve the log bits so they can be polled after
a warm reset, set this bit to 1.
Note: Reset by PWROK, not LDTRESET_L.
INTx_PACKET_EN. Read-Write.
Default = 0.
Reserved.
PARKATHOST. Read-Write. This bit controls the parking behavior of the AMD-8132™ tunnel internal
PCI/PCI-X
SHPC_PI_1. SHPC Programming Interface 1. If this bit is set, the AMD-8132 tunnel uses an SHPC
Programming Interface (PI) of 1 instead of 2 and provides the functions and CSRs associated with
PI = 1 instead of PI = 2. Intended for use with older SHPC device drivers which do not support
SHPC PI = 2.
Note: The value of this bit should not be changed after any SHPC commands have been issued. If it does
PCIX100. Read-Write. If this bit is set, PCI-X
X mode 2 operates at 200 MHz instead of 266 MHz. The default value of this bit is determined by
straps on PCIXA_100 for DevA:0x48[PCIX100] and PCIXB_100 for DevB:0x48[PCIX100].
If the value of this bit or Dev[B,A]:0x48[PSLOW_L] is written to after initial power-up, this change only
affects the PCI/PCI-X clock through the following sequence:
• If this bit is asserted (0), it causes the following PCI/PCI-X
• If this bit is deasserted (1), the log bits remain set until cleared by software or a PWROK
• When this CSR is set, transitions on the pins [B,A]_PIRQ[D,C,B,A]_L create INTx virtual wire
• When this CSR is cleared, no INTx virtual wire packets are generated.
• When asserted, the arbiter grants the PCI/PCI-X bus to the AMD-8132 tunnel when there is no
• When deasserted, the bus remains granted to the last bus master when there is no request.
• This bit has no effect in external arbiter mode, Dev[B,A]:0x48[EXTARB_L] = 0.
1. Write the new value to Dev[B,A]:0x48[PCIX100] or Dev[B,A]:0x48[PSLOW_L]; this will not directly
2. Set Dev[B,A]:0x3C[SBRST]; this will cause the clock frequency to change to the new value.
3. Wait at least 1 ms to allow the PCI devices to lock to the new clock frequency.
4. Clear Dev[B,A]:0x3C[SBRST].
after they are set: Dev[B,A]:0x80[SCM_PAR_ERR], Dev[B,A]:0x80[ADDR_OR_ATTR_ERR], and
Dev[B,A]:0x80[DISCARDED_POST].
deassertion.
packets as specified in HyperTransport™ I/O Link Specification, Rev 2.0.
request asserted.
modify the PCI clock speed.
change, results are undefined.
®
arbiter.
®
2.0 Tunnel Data Sheet
Registers
®
Mode 1 operates at 100 MHz instead of 133 MHz; PCI-
®
bus log bits to get cleared immediately
26792 Rev. 3.07 July 2005
Chapter 3