AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 48

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
48
Pin Name. Description
[B,A]_PCIXCAP. PCI-X
PCI bus. The state of this signal is captured during a cold reset at the rising edge of
LDTRESET_L (see section 4.2.1). After LDTRESET_L is deasserted, the state of
[B,A]_PCIXCAP is ignored. The state of this signal is recaptured at any cold reset but is not
recaptured during warm resets.
Alternate Function:
If hot-plug is enabled for this bus, [B,A]_PCIXCAP is the hot-plug input data from either the
TPS2342 or TPS2340A.
[B,A]_PCLK[4:0]. These are the PCI-X
See section 4.2.3 for bus frequency selection.
• [B,A]_PCLK[3:0] can be used as slot/device PCI clocks.
• [B,A]_PCLK[4] can also be used as a slot/device PCI clock, unless this bus is in single-slot
Alternate Function:
• If Dev[B,A]:0x48[HPEN] is asserted and Dev[B,A]:0x40[SSS_L] is asserted (low),
• If Dev[B,A]:0x48[HPEN] is not asserted and Dev[B,A]:0x40[SSS_L] is asserted (low),
[B,A]_PERR_L. PCI-X uncorrectable error.
[B,A]_PIRQ[A, B, C, D]_L. PCI-X
AMD-8132 tunnel.
• [B,A]_PIRQA_L can additionally be driven as an open-drain output in support of the hot-
• [B,A]_PIRQB_L can additionally be driven as an open-drain output in support of the
• [B,A]_PIRQC_L can additionally be driven as an open-drain output in support of the
• If TEST is high, A_PIRQC_L is used to indicate test mode. See section 2.6.
[B,A]_PLLCLKO. PLL clock output, see section 4.1 for details.
[B,A]_PLLCLKI. PLL clock input, see section 4.1 for details.
mode: Dev[B,A]:0x40[SSS_L] is asserted (low).
[B,A]_PCLK[4] is used as the hot-plug BUSEN_L input from either the TPS2342 or
TPS2340A.
[B,A]_PCLK[4] is used as VIO[B,A]_OVERRIDE_DELAY (see section 7.1.4).
plug controller.
[B,A]_Fatal signal.
[B,A]_Nonfatal signal.
®
frequency capabilities selection; used to determine the mode of the
®
interrupt requests; these are all inputs to the
®
®
clock outputs. The maximum frequency is 133 MHz.
2.0 Tunnel Data Sheet
Signal Descriptions
26792 Rev. 3.07 July 2005
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