AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 85

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 3
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SCF25. Read Only. This bit can be used to determine the actual PCI clock speed, used in conjunction
with Dev[B,A]:0x40[CPCI66] and Dev[B,A]:0x60[SCF].
The value of this register is determined by the value in Dev[B,A]:0x48[PSLOW_L], but the value in
Dev[B,A]:0x48[SCF25] is not updated until after the sequence described in Dev[B,A]:0x48[PCIX100].
Reserved.
PSLOW_L. Read-Write. If this bit is 0, conventional PCI runs at either 25 MHz or 50 MHz instead of
33 MHz or 66 MHz; 66 MHz PCI-X
unaffected by this bit, see section 4.2.2. This bit generally defaults to 1 at cold reset, unless the
following is detected on A_COMPAT:
If A_COMPAT is high at the rising edge of PWROK, stays high for at least an additional 120 ns and
then goes low prior to LDTRESET_L deassertion, Dev[B,A]:0x48[PSLOW_L] defaults to 0. If the value
of A_COMPAT or Dev[B,A]:0x48[PSLOW_L] is written to after initial power-up in non hot-plug mode,
this change only affects the PCI/PCI-X clock through the following sequence:
If the PCI bus is in hot-plug mode and needs to be run at 25 MHz or 50 MHz, then software should
write 0 to PSLOW_L after initial powerup and before writing to SHPC[B,A]:0x0C[NSI]. The frequency
change occurs immediately and software should wait 1 ms to allow the PCI devices to lock the new
clock frequency.
Note: The state of this signal is captured during a cold reset at the rising edge of LDTRESET_L (see section
Reserved.
Note:
Reserved.
Note:
Reserved.
Note:
EXTARB_L. Read-Write. Setting this bit to 0 allows the use of an external PCI/PCI-X
HPSIL_L controls the default state for both DevA:0x48[EXTARB_L] and DevB:0x48[EXTARB_L].
Note: This bit is not affected by LDTRESET_L.
Hot-Plug Enable [HPEN]. Read Only. This bit captures and inverts the state of [B,A]_REQ_L4 at the
rising edge of PWROK.
0 = Hot-plug mode is not enabled on this bridge.
1 = Hot-plug mode is enabled on this bridge. See section 1.3.7.
Note: This bit is not affected by LDTRESET_L.
• If this bit is set, then when Dev[B,A]:0x60[SCF] = 0, the clock speed is 25 or 50 rather than 33 or
• When Dev[B,A]:0x60[SCF] is 1 or 5, the clock speed is 50 rather than 66.
• If HPSIL_L is 1 at the rising edge of PWROK, then EXTARB_L is reset to 1.
• If HPSIL_L is 0 at the rising edge of PWROK, then EXTARB_L is reset to 0.
1. Write the new value to Dev[B,A]:0x48[PCIX100] or Dev[B,A]:0x48[PSLOW_L]; this will not directly
2. Set Dev[B,A]:0x3C[SBRST]; this will cause the clock frequency to change to the new value.
3. Wait at least 1 ms to allow the PCI devices to lock to the new clock frequency.
4. Clear Dev[B,A]:0x3C[SBRST].
66.
modify the PCI clock speed.
4.2.1). The state of this signal is recaptured at any cold reset but is not recaptured during warm resets.
®
runs at 50 MHz instead of 66 MHz. Higher PCI-X speeds are
AMD-8132™ HyperTransport™ PCI-X
Registers
®
2.0 Tunnel Data Sheet
®
arbiter.
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