AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 144

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Figure 19. Systemboard Clocking
4.1.2
Internal clocks may be disabled during power-managed system states such as power-on suspend. It is required
that all upstream requests initiated by the AMD-8132 tunnel be suspended while in this state.
To enable clock gating, DevA:0xF0[ICGSMAF] is programmed to the values in which clock gating is enabled.
STOP_GRANT cycles and STPCLK deassertion link broadcasts interact to define the window in which the
AMD-8132 tunnel is enabled for clock gating during LDTSTOP_L assertions. The system is placed into
power-managed states by steps that include a broadcast over the links of the STOP_GRANT cycle that
includes the System Management Action Field (SMAF) followed by the assertion of LDTSTOP_L.
When the AMD-8132 tunnel detects the STOP_GRANT broadcast enabled for clock gating, it enables clock
gating for the next assertion of LDTSTOP_L. While exiting the power-managed state, the system is required to
broadcast a STPCLK deassertion message. The AMD-8132 tunnel uses this message to disable clock gating
during LDTSTOP_L assertions. This is important because an LDTSTOP_L assertion is not guaranteed to
occur after the STOP_GRANT broadcast is received. The clock gating window must be closed to insure that
clock gating does not occur during STOP_GRANT for LDTSTOP_L assertions that are not associated with the
power states specified by DevA:0xF0[ICGSMAF]. Only a single LDTSTOP_L assertion may occur during the
window. So, to summarize:
144
STOP_GRANT broadcasts with SMAF fields specified by DevA:0xF0[ICGSMAF] enable the clock gat-
ing window and STPCLK deassertion broadcasts disable the window. If LDTSTOP_L is asserted while the
clock gating window is enabled, then clock gating occurs.
All PCI
signals
bus
Outgoing
flops
Clock Gating
Q
Incoming
flops
D
Internal PCI Clock
AMD 8132
®
PLLCLKI
2.0 Tunnel Data Sheet
Clocks and Reset
flight time
feedback
TM
PLL
Bridge
PLLCLKO
Phase Compensation
Phase Interpolator
flight time
PCLK
A_PCLK[4:0]
PCI device
26792 Rev. 3.07 July 2005
External
PCLK source
PCLK destination
Chapter 4