AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 80

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
80
25
24
23
22
21
20:16
15
14
13
MSIErrorNonfatalEn. Read-Write. Resets to 0. When this bit is set, it causes a nonfatal error interrupt
to be issued whenever Dev[B,A]:0x80[DROPPED_MSI] is asserted.
MSIErrorFatalEn. Read-Write. Resets to 0. When this bit is set, it causes a fatal error interrupt to be
issued whenever Dev[B,A]:0x80[DROPPED_MSI] is asserted.
PCIErrorNonfatalEn. Read-Write. Resets to 0. When this bit is set, it causes a nonfatal error interrupt
to be sent whenever one of the error conditions listed in the description of PCIErrorSerrDisable
occurs.
PCIErrorFatalEn. Read-Write. Resets to 0. When this bit is set, it bit causes a fatal error interrupt to
be sent whenever one of the error conditions listed in the description of PCIErrorSerrDisable occurs.
PCIErrorSerrDisable. Read-Write. Resets to 0. When this bit is set, it prevents errors detected on the
secondary bus from causing HyperTransport™ sync flood. The gated errors are:
PCLKEN[4:0]. Read-Write. Each of these bits controls a [B,A]_PCLK[4:0] signal. Bit 16 controls
PCLK 0, bit 17 controls PCLK1, and so forth.
0 = The PCLK signal is forced low. The intended use is to disable PCLK signals that correspond to
1 = The PCLK signal is enabled to toggle.
Reserved.
DIS64. Read-Write. If this bit is a 1, the AMD-8132 tunnel only generates and responds to
transactions on this PCI bus as a 32-bit device. The AMD-8132 tunnel never asserts [B,A]_REQ64_L
in the address phase and never asserts [B,A]_ACK64_L while asserting [B,A]_DEVSEL_L.
DISPU. Read-Write. If this bit is a 1, internal pullups on this PCI bus are disabled and external pullups
must be provided.
• Address or attribute phase uncorrectable error while the AMD-8132 tunnel is a potential target of
• Detecting a master abort, qualified by Dev[B,A]:0x3C[MARSP]; target abort, or PERR_L assertion
• Detecting a master abort, qualified by Dev[B,A]:0x3C[MARSP], or target abort while the
• Detecting an uncorrectable error while the AMD-8132 tunnel is the target of a split completion
• The secondary discard timer timed out, qualified by Dev[B,A]:0x3C[DTSE]. Indicated by the
the operation and secondary parity error response is enabled. Indicated by the assertion of
Dev[B,A]:0x80[ADDR_OR_ATTR_ERR], qualified with Dev[B,A]:0x3C[PEREN].
,qualified by Dev[B,A]:0x3C[PEREN], while the AMD-8132 tunnel is the master for a posted write
operation. Indicated by the assertion of Dev[B,A]:0x80[DISCARDED_POST].
AMD-8132 tunnel is the master for a split completion operation. Indicated by the assertion of
Dev[B,A]:0x60[SCD].
message, qualified by Dev[B,A]:0x3C[PEREN]. Indicated by the assertion of
Dev[B,A]:0x80[SCM_PAR_ERR].
assertion of Dev[B,A]:0x3C[DTS].
unimplemented PCI-X
®
devices or slots.
®
2.0 Tunnel Data Sheet
Registers
26792 Rev. 3.07 July 2005
Chapter 3