AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 47

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 2
Pin Name. Description
[B,A]_GNT_L[4,1,0]. PCI-X
[B,A]_GNT_L[3,2] do not exist as separate signals. These signals are shared with
[B,A]_ECC[5,4]. See section 2.6.
[B,A]_GNT_L4. This signal is an input while PWROK is low (strapping function). At all other
times this signal is a PCI grant output. This signal is only used as a grant output if the
following three conditions are true:
Alternate Function:
If Dev[B,A]:0x48[HPEN] is asserted and DevA:0x48[HP_IS_TPS2342] is not asserted, this is
[B,A]_HPSORLC. See section 2.6.
Strapping Function:
This signal must be pulled high to indicate multiple slots on this bus, or low to indicate a
single slot on this bus. See section 2.5.
[B,A]_GNT_L1. This signal is an input while PWROK is low (strapping function). At all other
times this signal is a PCI grant output. This signal is only used as a grant output if the
following two conditions are true:
Alternate Function:
This signal has two alternate functions. In external arbiter mode, it is a PCI request output
from the AMD-8132 tunnel. In single slot mode, it is the IDSEL signal for the single external
device. See section 2.6.
[B,A]_GNT_L0. This signal is an input while PWROK is low (strapping function). At all other
times this signal is a PCI grant output. This signal is only used as a grant output if the internal
PCI arbiter is used: Dev[B,A]:0x48[EXTARB_L] is not asserted (low).
Alternate Function:
In external arbiter mode this is a PCI request output from the AMD-8132 tunnel.
[B,A]_IRDY_L. PCI-X
[B,A]_M66EN. Frequency select input for [B,A]_PCLK while in conventional PCI mode.
When not in hot-plug mode, the state of this signal is captured at the rising edge of
[B,A]_RESET_L, see section 4.2.3. After the corresponding [B,A]_RESET_L signal goes
high, the state of [B,A]_M66EN is ignored. In hot-plug mode, this signal may be driven low as
an output after initialization.
[B,A]_PAR__ECC0. This is the PCI parity signal.
Multiple Use:
This signal is used as [B,A]_ECC[0] during PCI-X ECC mode.
[B,A]_PAR64__ECC7. This is the PCI upper 32-bit parity signal. The pullup to VIO is only
enabled if not in PCI-X Mode 2.
Multiple Use:
This signal is used as [B,A]_ECC[7] during PCI-X ECC mode.
1. The internal PCI arbiter is used: Dev[B,A]:0x48[EXTARB_L] is not asserted (low).
2. Hot-plug is not enabled for this bus: Dev[B,A]:0x48[HPEN] is not asserted.
3. Single slot mode is not enabled for this bus: Dev[B,A]:0x40[SSS_L] is not asserted (low).
1. The internal PCI arbiter is used: Dev[B,A]:0x48[EXTARB_L] is not asserted (low).
2. Single slot mode is not enabled for this bus: Dev[B,A]:0x40[SSS_L] is not asserted (low).
®
initiator ready signal.
®
grant signals.
Signal Descriptions
AMD-8132™ HyperTransport™ PCI-X
®
2.0 Tunnel Data Sheet
I/O
(See
left)
I/O
IOD
I/O
I/O
Type
Cell
I/O
V33
w/PU to
V33
V33
VIO
w/PU to
VIO
Power
Plane
47