AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 129

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 3
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Count Read Responses / Count Discards.
Default = 0
Note: If Control[1] = 0, this bit is affected by Control[9:7].
Count Nonposted Writes / Count Chained Posts.
Default = 0
Note: If Control[1] = 0, this bit is affected by Control[9:7].
Count Posted Writes / Count Inbound Read Latency.
Default = 0
Note: If Control[1] = 0, this bit is affected by Control[9:7].
Count Data Words / Count Wait State PCLKs.
Default = 0
Note: If Control[1] = 0, this bit affects Control[17:10].
Bridge Destination / Count Idle PCLKs.
Default = 0
Note: If Control[1] = 0, this bit affects Control[17:10].
• If Control[1] = 0 and this bit is set to 0, counting read response commands is disabled.
• If Control[1] = 1 and this bit is set to 0, counting discards is disabled.
• If Control[1] = 0 and this bit is set to 0, counting nonposted write or RMW commands is disabled.
• If Control[1] = 1 and this bit is set to 0, counting chained posts is disabled.
• If Control[1] = 0 and this bit is set to 0, counting posted write commands is disabled.
• If Control[1] = 1 and this bit is set to 0, counting inbound read latency is disabled.
• If Control[1] = 0 and this bit is set to 0, counting commands is enabled.
• If Control[1] = 1 and this bit is set to 0, counting wait state PCLKs is disabled.
• If Control[1] = 0 and this bit is set to 0, counting operations whose destination is the GPI is
• If Control[1] = 1 and this bit is set to 0, counting idle PCLKs (no FRAME/IRDY/TRDY) is disabled.
If Control[1] = 0 and this bit is set to 1, counting read response commands is enabled. Any
combination of Control[17:10] can be set, the count will be the total for all operations selected.
If Control[1] = 1 and this bit is set to 1, counting the amount of discarded data (0h to Fh) is enabled
for every PCLK where prefetched data gets discarded.
If Control[1] = 0 and this bit is set to 1, counting nonposted write or RMW commands is enabled.
Any combination of Control[17:10] can be set, the count will be the total for all operations selected.
If Control[1] = 1 and this bit is set to 1, counting chained posts is enabled. The count is the number
of packets (2, 3, or 4) chained together when a chained post transfers its first data on PCI/PCI-X
If Control[1] = 0 and this bit is set to 1, counting posted write commands is enabled. Any
combination of Control[17:10] can be set, the count will be the total for all operations selected.
If Control[1] = 1 and this bit is set to 1, counting inbound read latency is enabled.
If Control[1] = 0 and this bit is set to 1, counting the data words associated with the commands
selected in Control[17:10] is enabled.
If Control[1] = 1 and this bit is set to 1, counting wait state PCLKs is enabled.
disabled.
If Control[1] = 0 and this bit is set to 1, counting operations whose destination is the GPI is
enabled.
If Control[1] = 1 and this bit is set to 1, counting idle PCLKs (no FRAME/IRDY/TRDY) is enabled.
AMD-8132™ HyperTransport™ PCI-X
Registers
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2.0 Tunnel Data Sheet
129
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