AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 74

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
The links support 25 bits of I/O space. PCI-X supports 32 bits of I/O space. Host accesses to the link-defined
I/O region are mapped to the PCI-X I/O window with the 7 MSB always zero. PCI-X I/O accesses in which
any of the 7 MSBs are other than zero are ignored. The PCI-X I/O space window is defined as follows:
PCI-X IO window =
{Dev[B,A]:0x30[31:16], Dev[B,A]:0x1C[15:12], 12'hFFF} >= {7'h00,address[24:0]} >=
{Dev[B,A]:0x30[15:0],
The links and PCI-X support 40 bits of non-prefetchable memory space. The PCI-X non-prefetchable memory
space window is defined as follows:
PCI-X non-prefetchable memory window =
{24'h00, DevA:0xD8[15:8], Dev[B,A]:0x20[31:20], 20'hF_FFFF} >= address >=
{24'h00, DevA:0xD8[7:0],
The links and PCI-X support 64 bits of prefetchable memory space. All link memory mapped I/O space may be
within the PCI-X prefetchable memory window. The PCI-X prefetchable memory space window is defined as
follows:
PCI-X prefetchable memory window =
{Dev[B,A]:0x2C[31:0], Dev[B,A]:0x24[31:20], 20'hF_FFFF} >= address >=
{Dev[B,A]:0x28[31:0], Dev[B,A]:0x24[15:4],
These windows may also be altered by Dev[B,A]:0x3C[VGAEN, ISAEN].
When the address from either the host or a secondary bus master is inside one of the windows, then the
transaction is assumed to be intended for a target that sits on the secondary bus. Therefore, the following
transactions are possible:
For example: if IOBASE > IOLIM and Dev[B,A]:0x3C[VGAEN] is 0, then no host-initiated I/O space
transactions are forwarded to the secondary bus and all secondary PCI bus-initiated I/O space (not
configuration) transactions are forwarded to the host. If MEMBASE > MEMLIM and PMEMBASE >
PMEMLIM and Dev[B,A]:0x3C[VGAEN] is 0, then no host-initiated memory space transactions are
forwarded to the secondary bus and all secondary PCI bus-initiated memory space transactions are forwarded
to the host.
The windows may be overridden for compatibility traffic, enabled by DevA:0x48[COMPAT] as defined in the
HyperTransport
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• Host-initiated transactions inside the windows are routed to the secondary bus.
• Secondary PCI-initiated transactions inside the windows are not claimed by the AMD-8132 tunnel.
• Host-initiated transactions outside the windows are passed through the tunnel or master aborted if the
• Secondary PCI-initiated transactions outside the windows are claimed by the AMD-8132 tunnel and
AMD-8132 tunnel is at the end of a chain.
passed to the host.
TM
I/O Link Specification, Rev 2.0.
Dev[B,A]:0x1C[7:4],
Dev[B,A]:0x20[15:4],
®
2.0 Tunnel Data Sheet
Registers
20'h0_0000};
12'h000};
20'h0_0000};
26792 Rev. 3.07 July 2005
Chapter 3