AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 94

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
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2
1
0
Additional Uncorrectable ECC Error. Write 1 to clear. This bit is set if the bridge detects an
uncorrectable ECC error while already indicating some other ECC error (i.e., the ECC Error Phase
register is non-zero). Once set, this bit remains set until software writes a 1 to this location.
0 = No additional uncorrectable ECC error detected.
1 = One or more additional uncorrectable ECC errors detected.
Note: This register is cleared by PWROK, not by LDTRESET_L.
Additional Correctable ECC Error. Write 1 to clear. This bit is set if the bridge detects a correctable
ECC error while already indicating some other ECC error (i.e., the ECC Error Phase register is non-
zero). Once set, this bit remains set until software writes a 1 to this location.
0 = No additional correctable ECC error detected.
1 = One or more additional correctable ECC errors detected.
Note: This register is cleared by PWROK, not by LDTRESET_L.
Error Present in Other ECC Register Bank. Read Only. If this bit = 1, the ECC error logging
registers for the other interface hold information about an ECC error.
Note: This register is cleared by PWROK, not by LDTRESET_L.
Select Secondary ECC Registers. Read-Write. There is a single Select Secondary ECC Registers
bit that controls reading and writing of both primary and secondary ECC registers in the bridge.
• If the Select Secondary ECC Registers bit is 1, the primary ECC error logging registers hold
• If the Select Secondary ECC Registers bit is 0, the secondary ECC error logging registers hold
• If this bit is 1, reading from the ECC error logging registers (ECC Control and Status, ECC First
• If the bit is 1 in the data written to the ECC Control and Status register, the ECC Control and Status
• If this bit is 0, reading from the ECC error logging registers reads the values latched for the primary
• If this bit is 0 in the data written to the ECC Control and Status register, the ECC Control and
information about an ECC error for the primary interface. Since the primary bus is
HyperTransport™ and not PCI-X
information about an ECC error for the secondary interface.
Address, ECC Second Address, and ECC Attribute registers) reads the values latched for the
secondary interface.
register for the secondary interface is affected.
interface. Since the primary interface is HyperTransport™ and not PCI-X
ECC error on the primary interface.
Status register for the primary interface is affected. Since the primary interface is HyperTransport,
there are no relevant ECC registers.
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2.0 Tunnel Data Sheet
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, this is always 0.
Registers
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26792 Rev. 3.07 July 2005
, there will never be an
Chapter 3