AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 160

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
generation through the PIRQB/PIRQC RDRs, NIOAIRQB_L/NIOAIRQC_L assertion, or a HyperTransport
INTx Virtual Wire Message packet.
5.3.3
5.3.3.1
Assertion of PERR# by the AMD-8132 tunnel is enabled by Dev[B,A]:0x3C[16] Uncorrectable Error
Response Enable (PEREN) in the appropriate Bridge Control CSR. This assertion always causes the
Dev[B,A]:0x80[0] PERR_OBSERVED bit to be set, which may result in other actions.
5.3.3.2
Whenever the AMD-8132 tunnel signals a target abort on a PCI/PCI-X bus, it sets the Dev[B,A]:0x1C[27]
Signalled Target Abort (STA) bit in the appropriate Secondary Status CSR.
5.3.3.3
The AMD-8132 tunnel is capable of generating one class of split completion error message: PCI-X Bridge
Errors (Class 1). It is capable of generating all three message types: Master Abort, Target Abort, and
Uncorrectable Write Data Error. When the AMD-8132 tunnel issues a Target Abort message, it sets the
Dev[B,A]:0x1C[27] Signalled Target Abort (STA) bit in the appropriate Secondary Status CSR.
5.3.3.4
Based on bus mode and data width, the AMD-8132 tunnel is capable of appropriately poisoning data it returns
to the PCI/PCI-X bus by driving bad parity or ECC as follows:
160
• Parity, 32-bit: force bad PAR value on all data beats.
• Parity, 64-bit: force bad PAR, PAR64 values on all data beats.
• ECC, 32-bit: 7-bit ECC w/PEL inserted on all beats. For more about PEL, see PCI-X Protocol Addendum
• ECC, 64-bit: 8-bit ECC w/PED inserted on all beats. For more about PED, see PCI-X Protocol Addendum
to the PCI Local Bus Specification, Rev 2.0a.
to the PCI Local Bus Specification, Rev 2.0a.
PCI/PCI-X
PERR# Assertion
Target Aborts
Split Completion Error Messages
Data Poisoning
®
Interface
Error Conditions and Handling
®
2.0 Tunnel Data Sheet
26792 Rev. 3.07 July 2005
Chapter 5