LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 134

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

8-8
R
LVD
SPEN
EIEN
Register: 0xFF08
Multipurpose I/O Bank 0 Output (MPO0)
Read/Write
MPO0_
System Registers
7
0
0
Reserved
SCSI LVD Mode (read only)
This read only bit is set when the SCSI interface is in LVD
mode.
Serial Port Enable
When this bit is set to 1, the MPIO3_2 pin is mapped to
the TXD serial port function of the microcontroller core
and the MPIO3_3 pin is mapped to the RXD serial port
function of the microcontroller core. When cleared (0), the
MPIO3_2 and MPIO3_3 pins are controlled as standard
multipurpose I/O pins. The
Enable (MPE3)
registers for MPIO bank 3 are not used in controlling the
serial port function of the microcontroller core.
External Interrupt Enable
When this bit is set to a 1, the MPIO3_0 pin is mapped
to the INT0/ external interrupt function of the
microcontroller core and the MPIO3_1 pin is mapped to
the INT1/ external interrupt function of the microcontroller
core. When cleared (0), the MPIO3_0 and MPIO3_1 pins
are controlled as a standard multipurpose I/O pin. The
Multipurpose I/O Bank 3 Enable (MPE3)
(0xFF21) and other control registers for MPIO bank 3 are
not used in controlling the serial port function of the
microcontroller core.
Multipurpose I/O Bank 0 Output
The values stored in these register bits are driven on the
I/O pins MPIO0_0, MPIO0_1, MPIO0_2, MPIO0_3,
MPIO0_4, MPIO0_5, MPIO0_6, and MPIO0_7 when the
corresponding pin enable in register 0xFF09 is set.
0
0
register (0xFF21) and other control
MPO0_
0
Multipurpose I/O Bank 3
0
register
0
0
0
[6:3]
[7:0]
2
1
0