LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 23

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.3 SCSI Core Operation
2.3.1 Recommended Use of SCSI High ID Pins
0xFBFF
0x3FFF
0xFC00
0xFFFF
Figure 2.2
The address decode block in the LSI53C040 decodes addresses
generated by the microcontroller and multiplexes memory space
accesses between the different register and memory blocks according to
the memory map.
The LSI53C040 uses a SCSI core based on the LSI53C80 first
generation SCSI architecture. The LSI53C80 architecture supports
8-bit, asynchronous only SCSI data transfers. It supports both SE and
LVD SCSI transfers. The core contains support for parity generation and
checking, initiator and target operation, arbitration, and interrupts to the
microcontroller. The core is controlled by several registers that are
described in
The SCSI core in the LSI53C040 is designed for 8-bit SCSI applications
only. However, the LSI53C040 contains some additional logic that allows
the device to have three SCSI high IDs, in addition to 0–7, so that the
LSI53C040 can be given lower priority on a wide SCSI bus. However, the
LSI53C040 cannot perform selection or reselection on a wide bus; parity
SCSI Core Operation
0x0000
0x0032
0x0033
0x4000
16 Kbytes Internal RAM
Features Registers
47 Kbytes External
Interrupt Vectors
1 Kbyte Internal
Address Space
Chapter
LSI53C040 Memory Map
4.
2-5