LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 80

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4-6
Register: 0xFC02
Mode (MR)
Read/Write
AS_LVD
TGTM
EPC
EPI
R
MB
SCSI and DMA Registers
AS_LVD
7
0
TGTM
6
0
Arbitration/Selection LVD
This bit must be set to perform arbitration, selection, and
reselection, and must be cleared upon successful
completion of selection or reselection prior to asserting
the data bus for any information transfer phases. When
set, this bit causes the SCSI data bus to operate in open
drain mode, which is a requirement of LVD SCSI as
defined in the SPI-2 draft standard. Operation of this bit
does not effect SCSI SE mode.
Target Mode
The Target Mode bit allows the SCSI core to operate as
either a SCSI bus initiator (bit reset to 0) or as a SCSI
bus target device (bit set to 1). In order for the signals
ATN/ and ACK/ to be asserted on the SCSI bus, the
Target Mode bit must be reset (0). In order for the signals
C_D/, I_O/, MSG/ and REQ/ to be asserted on the SCSI
bus, the Target Mode bit must be set (1).
Enable Parity Checking
The Enable Parity Checking bit determines whether parity
errors will be ignored or saved in the parity error latch. If
this bit is reset (0), parity will be ignored. Conversely, if
this bit is set (1), parity errors will be saved.
Enable Parity Interrupt
The Enable Parity Interrupt bit, when set to a 1, causes
an interrupt to occur if a parity error is detected. A parity
interrupt will only be generated if the Enable Parity
Checking bit (bit 5) is also enabled.
Reserved
This bit must be cleared to 0.
Monitor Busy
The Monitor Busy bit, when set to a 1, causes an
interrupt to be generated for an unexpected loss of BSY/.
EPC
5
0
EPI
4
0
R
3
0
MB
2
0
DM
1
0
ARB
0
0
7
6
5
4
3
2