LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 50

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.10.5 Masking and Enabling Interrupts
2.10.6 Polling and Hardware Interrupts
2-32
The External Interrupt Enable bit (0xFD01/0xFD03, bit 3) enables the
interrupt output to the microcontroller, while the Pending Interrupt bit (bit 7)
is clear. The PIN bit is active when the Two-Wire Serial interface has
completed an operation and requires processor intervention to continue.
Table 2.5
testing purposes, certain types of interrupts can be forced by writing
individual bits in the
interrupts can be masked by clearing the corresponding bit in the
Interrupt Mask (IMR)
the corresponding bit in the ISR will be set if the interrupting condition
occurs.
Masking an interrupt prevents it from being seen by the microcontroller
core in the LSI53C040. You can allow hardware interrupts either by
enabling them in the appropriate register bits, or by masking the
interrupts and polling for them. In general, it is recommended to enable
as few interrupts as possible and mask/poll for them instead. With the
microcontroller and the serial transfer rates on the Two-Wire Serial bus,
masking and polling for interrupts is less disruptive to the microcontroller
and does not impede performance. An exception to this recommendation
would be SCSI and 8067 interrupts, since the bus speeds and the need
to complete transfers quickly suggest that interrupts should be enabled.
The microcontroller core is informed of an interrupt condition by polling
or hardware interrupts. Polling means that the microcontroller must
continually loop and read a register until it detects a bit set that indicates
an interrupt. This method is the fastest, but consumes microcontroller
time that could be used for other tasks. The other method for detecting
interrupts is hardware interrupts, where the interrupting condition asserts
one of the microcontroller external interrupt signals. This interrupts the
microcontroller, and causes it to execute an interrupt service routine. A
hybrid approach is common, using hardware interrupts for conditions that
might occur infrequently or after a long wait; and polling for interrupts that
typically occur after only a short wait.
Functional Description
lists the registers used for masking and enabling interrupts. For
Interrupt Status (ISR)
register (0xFE0D). Even if the interrupt is masked,
register (0xFE04). These