LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 29

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.3.4 SCSI - DMA Transfers
2.3.4.1 Halting a DMA Operation
In the LSI53C040, DMA handshaking with the SCSI core is handled
automatically by the DMA function. In order to initiate a DMA transfer to
the SCSI core using the DMA function in the LSI53C040, the following
sequence must be performed:
1. The
2. The
3. The firmware sets bit 0 in register 0x87 of the microcontroller core to
4. The DMA waits for the microcontroller to enter the idle mode before
5. Once the DMA receives a request from the SCSI core, the transfer
Figure 2.6
Any SCSI or DMA interrupt, if enabled in the
register, terminates the DMA cycle for the current bus phase. It is
recommended that the DMA Mode bit be reset after receiving an
interrupt. The DMA Mode bit must be set before writing any of the Start
DMA registers for subsequent bus phases.
SCSI Core Operation
Source/Destination Low (DSDL)
(DSDH)
(TIP) position.
place the core in idle mode.
taking over the internal bus for memory reads or writes.
begins.
DMA Status (DS)
DMA Transfer Length (DTL)
illustrates a target mode DMA transfer.
address registers (0xFC11–0xFC13) must be written.
register (0xFC10) is written with a 1 in the bit 0
and
register and the
DMA Source/Destination High
Interrupt Mask (IMR)
DMA
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