TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 128

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
11.11 HIGH ORDER ALARM INDICATION (RING) PORT INTERFACE
11.10.2 Receive High Order POH Port Interface
All received High Order Path Overhead bytes are sent over a serial Receive POH Port
interface. The values sent out on this interface are the raw, unprocessed values, except for
B3, where an error mask is calculated (ones indicates the errored bits).
The Receive POH Port consists of following leads:
The Receive POH Port protocol is as follows (see
Note: No configuration is necessary for this POH Port.
The High Order Alarm Indication (Ring) Port Interface transports the Remote Information (RI)
from the High Order POH sink/monitor to the POH source/generator. The Remote Information
consists of the REI and (enhanced) RDI values to be inserted by the POH generator.
The High Order POH monitor sends the Remote Information of all High Order path channels
to the Receive High Order Alarm Indication (Ring) Port Interface. This port multicasts the
information internally to the POH generator and externally to the Receive Alarm Indication
(Ring) Port Interface.
The source for the Remote Information can be selected in the POH generator, per high order
path. When the Remote Information is taken from the Transmit High Order Alarm Indication
(Ring) Port Interface, it is possible to configure the High Order Alarm Indication (Ring) Port
Interface to use the internally or externally available information.
When the ExtendRDI option is asserted, the RDI insertion will be extended to minimum 20
frames.
• Output Receive POH Port Clock POHRXCLK
• Output Receive POH Port Address Latch Enable POHRXALE
• Output Receive POH Port Address POHRXADDR
• Output Receive POH Port Data Latch Enable POHRXDLE
• Output Receive POH Port Data POHRXDATA
1. The 8-bit address for the transmitted byte is output on POHRXADDR, most significant
2. A one cycle gap is left open.
3. The 8-bit data of the transmitted TPOH byte is output on POHRXDATA. During this
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High Order Pointer Tracking, Retiming and Pointer Generation
bit first. During this time the Address Latch Enable POHRXALE is asserted.
time the Data Latch Enable POHRXDLE is asserted.
Figure
10):
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1 2 8 o f 2 0 2